The subject matter disclosed herein relates to integrated circuit devices. More particularly, the subject matter relates to fabrication of integrated circuit devices.
As integrated circuit technologies have advanced, the size of these devices has correspondingly decreased. In particular, as devices are reduced in scale to comply with ever-smaller packaging, tighter constraints are applied to their dimensions and spacings.
Integrated circuit (IC) chips are formed by fabricating a plurality of devices on a wafer, and dicing the wafer along kerf lines separating the devices, to form a plurality of individual chips. However, as IC chips have become thinner, the silicon-to-metal ratio in the kerf area of the wafers makes dicing of those chips more cumbersome, more time consuming and potentially damaging to the surrounding wafer.